1. Field of the Invention
The present invention relates to a semiconductor device including an output buffer circuit or an input/output buffer circuit, and more specifically, a semiconductor device in which a voltage that is higher than its own power supply voltage may be applied to the output terminal or the input/output terminal.
2. Description of Related Art
Recently, focusing on a semiconductor integrated circuit (hereinafter, referred to as LSI) having a CMOS construction, the drive power supply voltage of the LSI has become low due to miniaturization development. However, the transition to the lower voltage differs among LSIs product fields, so that when constructing a system, a plurality of LSI with different power supply voltages must be combined. Therefore, if possible, direct connection of terminals of LSIs that operate with power supply voltages different from each other is convenient. In this case, it must also be considered that a signal with a voltage amplitude different from the voltage amplitude of an output signal is applied to the terminal. Therefore, it is necessary that an undesirable leak current does not flow between the power supply voltages even when a signal with a voltage amplitude equal to or higher than that of the power supply voltages is applied from the exterior, and circuit systems have been conventionally proposed.
As a prior art, in the driver circuit disclosed in Japanese Published Unexamined Patent Application No. S64(1989)-72618, a circuit example in which no leak current flows even when a voltage higher than the power supply voltage VDD is applied from the exterior is proposed.
As shown in FIG. 11, in the driver circuit 100, to the NAND gate 11 and the NOR gate 12, an output data signal DOUT is inputted, and an output enable signal EN is inputted directly to the NAND gate 11 and inputted to the NOR gate 12 by being inverted through the inverter gate 160. The output terminals thereof are connected to the gate terminal G1 of the PMOS transistor P1 on the power supply voltage VDD side and the gate terminal of the NMOS transistor N1 having a source terminal connected to a ground voltage.
To the source terminal of the PMOS transistor P1, the power supply voltage VDD is inputted via the PMOS transistor P2, and the drain terminal of the NMOS transistor N1 is connected to the drain terminal of the PMOS transistor P1 via the NMOS transistor N2 having a gate terminal connected to a power supply voltage source VDD. This connection point is a terminal BUS.
In addition, the gate terminal G2 of the PMOS transistor P2 is connected to the NMOS transistor N6 via the NMOS transistor N4. The source terminal of the NMOS transistor N6 is connected to a ground voltage, and to the gate terminal, an output enable signal EN is inputted. To the gate terminal of the NMOS transistor N4, the power supply voltage VDD is inputted.
Furthermore, between the gate terminal G2 and the drain terminal of the PMOS transistor P2, a PMOS transistor P100 having a gate terminal to which the output enable signal EN is inputted is connected. Although illustration is omitted, it is also allowed that the gate terminal of the PMOS transistor P100 is connected to a power supply voltage VDD. The N well NW of the PMOS transistors P1, P2, and P100 is connected to the N well voltage control circuit 130 constructed of a PMOS transistor.
In the driver circuit 100, even when a voltage equal to or higher than a threshold voltage of the PMOS transistor is applied from the power voltage VDD to the terminal BUS, the PMOS transistor P2 maintains a nonconductive state and prevents a leak current from flowing to the power supply voltage VDD through the PMOS transistors P1 and P2 from the terminal BUS.
The prior art document referred to in the description given above is as follows.
However, this has a first problem shown in FIG. 12. In a case where an input/output buffer circuit 110 to which an input signal with a voltage higher than its own power supply voltage VDD may be inputted through the terminal BUS is constructed by adding an input buffer circuit 400 to the drive circuit 100, when the operation mode switches from an output buffer mode to an input buffer mode, and the input signal with a voltage higher than the power supply voltage VDD is inputted, a problem may occur.
As the output enable signal EN being at the high level in the output buffer mode goes low, the input buffer mode is started. When the output enable signal EN goes low, the NMOS transistor N6 becomes nonconductive. As a result, the transistor that drives the gate terminal G2 of the PMOS transistor P2 disappears, and the terminal G2 floats. In this case, since the level of the gate terminal voltage VG2 immediately before this event is low, the terminal G2 maintains the low voltage level even after switching to the input buffer mode. The gate terminal voltage of the PMOS transistor P100 becomes the ground voltage, and the gate terminal voltage VG1 of the PMOS transistor P1 becomes the power supply voltage VDD. In some cases, the gate terminal of the PMOS transistor P100 is connected to a power supply voltage VDD.
In this state, when, from the terminal BUS, a voltage signal VDDex higher than the threshold voltages of the PMOS transistors is inputted from the power supply voltage VDD, the PMOS transistor P1 conducts it. Herein, when the gate terminal of the PMOS transistor P100 is at the ground voltage, the PMOS transistor P100 maintains the conductive state, and even when the gate terminal of the PMOS transistor P100 is connected to a power supply voltage VDD, the PMOS transistor P100 is conductive, so that the voltage level VG2 of the terminal G2 is charged to the voltage level to be externally inputted, however, rapid charging is not carried out due to a time constant caused by parasitic resistances and parasitic capacitances of the transistors and wiring.
Therefore, in some cases, in the charging transition period (T) of the voltage level VG2 of the terminal G2, the PMOS transistor P2 is maintained as conductive. In this case, a leak current IIN from the terminal BUS to the power supply voltage VDD is generated. This leak current IIN flows-in from the high voltage level VDDex connected to the interface circuit IF connected to the terminal BUS, the voltage is divided into an output resistance of the interface circuit IF and ON-resistances of the PMOS transistors P1 and P2, and the voltage level VBUS of the bus line BUS drops. When the dropped voltage becomes lower than the input threshold voltage of the buffer circuit Buf, the output voltage VX may not be outputted and is a problem.
A second problem is shown in FIG. 13. A voltage VDDex higher than the power supply voltage VDD is generated as an output voltage, and this may pose a problem when the output structure of the driver circuit 100 is tentatively used as an open drain structure of the NMOS transistor.
In the driver circuit 100, the ground voltage is supplied to a terminal to which the output data signal DOUT should be inputted and the output data signal DOUT is inputted to a terminal to which the output enable signal EN should be inputted.
In response to the output data signal DOUT at a high level, the driver circuit 100 becomes able to output, and outputs a low level signal fixed to the ground voltage. At this point, the PMOS transistor P1 maintains the conductive state, so that the voltage level VG2 of the gate terminal G2 is the ground voltage.
When the output data signal DOUT goes low, the driver circuit 100 becomes unable to output, and the PMOS transistor P1 and the NMOS transistor N1 both become nonconductive. Simultaneously, the NMOS transistor N6 also becomes nonconductive, and the terminal G2 floats while maintaining the low voltage level.
The bus line BUS that is not driven from the driver circuit 100 is charged to the external voltage VDDex by an external pull-up resistor Rup, however, this charging is not rapid due to parasitic resistances and parasitic capacitances.
When the voltage VBUS to be applied to the terminal BUS from the power voltage VDD becomes higher than the threshold voltage of the PMOS transistor, the PMOS transistor P1 becomes conductive and the terminal G2 is charged, however, since this charging is not rapid, during the charging transition period (T) of the voltage level VG2, the PMOS transistor P2 may be maintained as conductive. In this case, a leak current IIN from the terminal BUS to the power supply voltage VDD is generated. When a voltage drop of the bus line BUS due to this leak current IIN becomes lower than the input threshold voltage of the buffer circuit Buf, the output voltage VX may not be outputted and this is a problem.
The invention was made to solve at least one of the above-described conventional problems, and an object thereof is to provide a semiconductor device including an output buffer circuit or an input/output buffer circuit which can correctly maintain the terminal voltage without an undesirable leak current flow via terminals even when a voltage signal higher than its own power supply voltage is applied to the output terminal or the input/output terminal.